Semiconductor Thin-film Transistors Research Articles

Research on correlation between metal oxide semiconductor target and magnetron sputtered film based on TFT application

The research on the intrinsic relationship between target quality and TFT (thin film transistor) performance is not perfect for magnetron sputtering processes. The systematic analysis of target-film-device still needs to be improved. This paper studied the internal relationship between metal oxide semiconductor targets, thin films, and TFT devices for the deterioration problem of device performance caused by the failure of the aging target. The experimental results showed that the target surface with a long cumulative sputtering time had apparent macroscopic concave, related to the electromagnetic field distribution. The concave region was the primary source of thin film composition, so the research object of this work was mainly the concave region. A multi-oxide target was used in this work, and its selective sputtering phenomenon was serious, mainly reflected in the sputtering rate of In2O3 grains with higher electrical conductivity than other components. There were many failure sites on the surface of the target, including nodules, holes, coating layers, and cracks. The failure sites would hinder the normal sputtering process and eventually form a vicious circle, failing the target. Due to the decline of target quality, sputtering particles would be in a state of insufficient kinetic energy, resulting in particle agglomeration, element segregation, weak M-O (metal-oxide) bonds, loose accumulation, and surface or block defects. Ultimately, the TFT performance with the aging target showed lower mobility, larger subthreshold swing, increased off-state current, and poorer stability. Clarifying the relationship between target quality and device performance is beneficial for the development of electronic devices.

Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors

In this work, models of p-type CuO metal-oxide- semiconductor (MOS) capacitor and thin-film transistors (TFTs) are established using numerical simulation tools and compared with experimental data, to investigate the impact of a passivation layer on the TFT subthreshold behavior. Simulated transfer curves and hole concentrations of back-gated CuO TFT with 10 μm channel length confirm the experimental observation of buried-channel and accumulation-mode conduction mechanisms. The subthreshold behavior is analyzed with HfO2 passivation on the top CuO surface varying the densities of fixed oxide charge and interface states, as well as the thickness of the CuO film. The simulation results demonstrate a significant potential improvement of the subthreshold slope and on/off current ratio, mainly thanks to the optimization of the fixed oxide charge densities.

Pentacene to Octacene: The Limit of Fourfold TIPS-Ethynylation

Soluble acenes beyond hexacene are rare. Their sensitivity complicates isolation, purification and application in devices. To increase the stability of acenes, functionalization with trialkylsilylethynyl substituents prevents [4 + 4] dimerization and oxidation. At the same time, such acenes are soluble and processible. Here we present the modular synthesis of fourfold tri-iso-propylsilylethynyl-ethynylated pentacenes to octacenes and investigate their optical and redox properties, frontier orbital positions (CV, density functional theory calculations) as well as their stability in solution (UV/vis, NMR spectroscopy). We also investigated their magnetic properties as a function of acene length. Pentacene, hexacene and heptacene are sufficiently stable to serve as semiconductors in thin-film transistors – the octacene rapidly decays to its butterfly dimer evidence by time-dependent NMR spectroscopy and crystal structure analysis.

Light Effect on Amorphous Tin Oxide Thin‐Film Transistors

Amorphous tin oxide (a‐SnOx) is a potential transparent oxide semiconductor candidate for future large‐area electronic applications. The thin‐film transistor (TFT) mobilities reach ≈100 cm2 Vs−1, a mobility higher than other multiple cation‐based oxide semiconductor TFTs. Few optical properties have been reported so far and therefore both the effect of visible light and negative bias illumination stress (NBIS) on a‐SnOx TFT performances, known to dramatically impact oxide semiconductor‐based TFTs, have been investigated. The variation of density of states (DOS) due to NBIS by device simulation is analyzed, and a fourfold increase of the donor‐like states and a decrease in the band edge DOS from 2.3 to 2.0 × 1019 cm−3 eV−1 are showed. The evaluation of the effect of neutral, singly, and doubly ionized oxygen vacancies by density functional theory using 95 atoms reveals not only states in the gap of SnO2, but also variations in the electron density, and modifications in the crystal parameters compared to a structure without an oxygen vacancy. Material and device simulation analysis reveal that the oxygen vacancies have a dramatical impact on the DOS in the gap of SnO2 and can explain the NBIS phenomenon observed in a‐SnOx TFT.

Deep-Submicron Channel Length Oxide Semiconductor Thin-Film Transistors Enabled by Self-Aligned Nanogap Lithography

Deep-Submicron Channel Length Oxide Semiconductor Thin-Film Transistors Enabled by Self-Aligned Nanogap Lithography

Facile diffusion of sulfur and fluorine into a-IGTO thin films for high-performance and reliability of transparent amorphous oxide semiconductor thin-film transistors

Facile diffusion of sulfur and fluorine into a-IGTO thin films for high-performance and reliability of transparent amorphous oxide semiconductor thin-film transistors

High Reliability Tungsten-Doped Indium Zinc Oxide Thin Film Transistors for Display Applications

Recently, flat panel display technologies are based on amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or amorphous oxide semiconductor (AOS) thin film transistors (TFTs) technology. In order to reach higher performance for ultra-high resolution display applications, the material selection for the channel layer is vital. AOS TFTs drawn lots of attention because of its advantages such as low leakage current, high driving current and high uniformity [1,3]. In this work, we presented a novel amorphous oxide semiconductor (AOS) material of gallium-free a-InWZnO thin film transistors (IWZO TFTs) which is very promising to be applied for ultra-high resolution display technology. Experiment In this work, we demonstrated the structure of a-IWZO TFTs processes. Figure 1 shows the schematic of the TFT cross-section. After growing a 550 nm thermal oxide layer as buffer layer, a 25-nm-thick of molybdenum was deposited by DC-sputter as the bottom gate electrode. A 10-nm-HfO2 was deposited by plasma-enhanced atomic layer deposition (PEALD) system as high-κ gate dielectric (GI). Then, post deposition annealing (PDA) was carried out to enhance the quality of the insulator layer. Next, an ultra-thin body a-IWZO was deposited by RF-sputter as channel layer. Finally, source and drain were defined by lift-off process and the gate contact via was etched by dry etching to finish the device fabrication. Result and Discussion Figure 1(b) shows the negative gate bias stress (NGBS) transfer curve (ID-VG) of a-IWZO TFTs with passivation layer. The experimental results have shown that passivation layer could keep the back channel of IWZO channel from exposing to oxygen and hydrogen from the atmosphere. Without the passivation layer, the back channel would contact moisture leading the diffused hydrogen atoms to fill oxygen vacancy sites and de-trap free carriers, causing the VTH shifts negatively. The ultra-thin a-IWZO TFTs with passivation layer exhibited a low subthreshold swing (S.S.) of 89.7 mV/dec, high on/off current ratio (ION/IOFF) of 2.1×107 and small threshold voltage shift (ΔVth) of -0.097 V during NGBS of -2MV/cm with 2000s. To sum up, the passivation layer could enhance the a-IWZO TFTs reliability. Reference [1] Kamiya, H. Hosono, NPG Asia Mater., vol. 2, pp. 15, 2010.[2] Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, nature, vol. 432, no. 7016, pp. 488-492, 2004.[3] Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019. Figure 1

Compositional tailoring of indium-free GZO layers via plasma-enhanced atomic layer deposition for highly stable IGZO/GZO TFT

Oxide semiconductor-based thin-film transistors (TFTs) are promising candidates for display backplanes and memory device applications. To achieve high device performance and sustain the electrical properties under prolonged operation, it is important to overcome the mobility–stability trade-off in oxide TFTs. Here, we propose a bilayer-structured semiconductor stack formed by plasma-enhanced atomic layer deposition (PEALD), where an indium-free gallium zinc oxide (GZO) film is grown on top of indium gallium zinc oxide (IGZO), to be implemented in top gate devices. Applying a GZO layer (with optimum Ga to Zn ratio) between the IGZO and the gate insulator (GI) resulted in two major effects: interface engineering and band alignment modulation. While maintaining a sufficiently large field effect mobility (31.9 cm2 V−1 s−1), considerable improvements in device reliability were observed concerning positive-bias thermal stress (PBTS) and negative-bias illumination stress (NBIS) compared to TFTs incorporating IGZO single layers. This suggests that proper composition control through PEALD in the bilayer oxide semiconductor TFT may help achieve an appropriate balance between mobility and reliability.

Machine Learning Driven Channel Thickness Optimization in Dual-Layer Oxide Thin-Film Transistors for Advanced Electrical Performance.

Machine learning (ML) provides temporal advantage and performance improvement in practical electronic device design by adaptive learning. Herein, Bayesian optimization (BO) is successfully applied to the design of optimal dual-layer oxide semiconductor thin film transistors (OS TFTs). This approach effectively manages the complex correlation and interdependency between two oxide semiconductor layers, resulting in the efficient design of experiment (DoE) and reducing the trial-and-error. Considering field effect mobility (𝜇) and threshold voltage (Vth ) simultaneously, the dual-layer structure designed by the BO model allows to produce OS TFTs with remarkable electrical performance while significantly saving an amount of experimental trial (only 15 data sets are required). The optimized dual-layer OS TFTs achieve the enhanced field effect mobility of 36.1cm2 V-1 s-1 and show good stability under bias stress with negligible difference in its threshold voltage compared to conventional IGZO TFTs. Moreover, the BO algorithm is successfully customized to the individual preferences by applying the weight factors assigned to both field effect mobility (𝜇) and threshold voltage (Vth ).

Enhancement of electrical performance in indium-zinc oxide thin-film transistors with HfO2/Al2O3 gate insulator deposited via low-temperature ALD

Several studies have been conducted on amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) with the aim of applying them to the next-generation low-power displays. To improve the electrical performance of conventional AOS TFTs, which are known for their poor switching characteristics, we fabricated indium-zin oxide (IZO) TFTs with HfO2/Al2O3 gate insulator deposited via low-temperature atomic layer deposition (ALD). We optimized the electrical performance of the fabricated TFTs by varying the thickness of the IZO channel and Al2O3 insulator, respectively. Compared to the samples with a thermally grown 150 nm thick SiO2 gate insulator, the samples with a 10 nm thick IZO channel and a 10/70 nm thick HfO2/Al2O3 gate insulator exhibited the subthreshold swing of 0.24 V/dec, saturation carrier mobility of 7.49 cm2/V∙s and on–off current ratio of 1.09 × 107, which were improved by more than 47 %, 64 % and 5 times, respectively. Also, the threshold voltage shift in positive and negative bias stress conditions were improved to + 0.90 and – 1.75 V, respectively.

Lifetime estimation of thin-film transistors in organic emitting diode display panels with compensation

Oxide semiconductor thin-film transistors (TFTs) are used in the pixel array and gate driver circuits of organic light emitting diode (OLED) display panels. Long-term reliability characteristics of the TFTs are a barometer of the lifetime of OLED display panels. The long-term reliability of the driver TFTs is evaluated in a short time under high voltages and high temperature for an accelerated degradation test. If reliability parameters from the power law or stretched-exponential functions are the same for individual devices and devices in an operating panel, the lifetime of the panel can be accurately estimated. However, since compensation circuits are designed into operating panels, an environmental discrepancy exists between the accelerated test of single devices and the operation of devices in the panel. Herein, we propose a novel compensation stretched-exponential function (CSEF) model which captures the effect of the threshold voltage compensation circuit in the panel. The CSEF model not only bridges the discrepancy between individual devices and panel devices, but also provides a method to accurately and efficiently estimate the long-term lifetime of all display panels that utilize compensation circuits.

Rapid and simultaneous multiple detection of a tripledemic using a dual-gate oxide semiconductor thin-film transistor-based immunosensor

The simultaneous infection with a tripledemic—simultaneous infection with influenza A pH1N1 virus (Flu), severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2), and respiratory syncytial virus (RSV)—necessitates the development of accurate and fast multiplex diagnostic tests. The coronavirus disease 2019 (COVID-19) pandemic has emphasized the importance of virus detection. Field-effect transistor (FET)-based immuno-biosensors have a short detection time and do not require labeling or polymerase chain reaction. This study demonstrates the rapid, sensitive detection of influenza A pH1N1, SARS-CoV-2, and RSV using a multiplex immunosensor based on a dual-gate oxide semiconductor thin-film transistor (TFT), a type of FET. The dual-gate oxide TFT was modified by adjusting both top and bottom gate insulators to improve capacitive coupling to approximately 120-fold amplification, exhibiting a high pH sensitivity of about 10 V/pH. The dual-gate oxide TFT-based immunosensor detected the target proteins (hemagglutinin (HA) protein of Flu, spike 1 (S1) protein of SARS-CoV-2, and fusion protein of RSV) of each virus, with a limit of detection of approximately 1 fg/mL. Cultured viruses in phosphate-buffered saline or artificial saliva and clinical nasopharynx samples were detected in 1-μL sample volumes within 60 s. This promising diagnosis could be potentially as point-of-care tests to facilitate a prompt response to future pandemics with high sensitivity and multiplexed detection without pretreatment.

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors (TFTs), severe instabilities and even hard breakdown under high-current stress (HCS) become critical challenges. In this work, the triggering voltage of HCS-induced self-heating (SH) degradation is defined in the output characteristics of amorphous indium-gallium-zinc oxide (a-IGZO) TFTs, and used to quantitatively evaluate the thermal generation process of channel donor defects. The fluorinated a-IGZO (a-IGZO:F) was adopted to effectively retard the triggering of the self-heating (SH) effect, and was supposed to originate from the less population of initial deep-state defects and a slower rate of thermal defect transition in a-IGZO:F. The proposed scheme noticeably enhances the high-current applications of oxide TFTs.

Silicon Phthalocyanines as Emerging n-Type Semiconductors in Thin Film Transistors

Silicon phthalocyanines are emerging n-type semiconductors for use in organic photovoltaics (OPVs) and organic thin-film transistors (OTFTs).[1] Their low synthetic complexity paired with their versatile axial group facilitates the finetuning of their chemical properties, solution properties and processing characteristics without significantly affecting their frontier orbital levels or their absorption properties. The crystal engineering and film forming characteristics of silicon phthalocyanine semiconductors can be tuned through appropriate axial group functionalization, therefore facilitating their integration into OTFTs by solution processing or vapor deposition.We were the first to integrate SiPcs into OTFTs, and unlike the majority of phthalocyanines, SiPcs are inherently better electron transporting materials then hole transport materials. We demonstrated n-type mobilities on the order of 0.5 cm2/Vs which is among the best of all phthalocyanines.[3] Through axial functionalization we reported that changes in the electron withdrawing character of the axial group lead to predictable drops in device threshold voltage from 45 V to 5 V.[4] The axial group can also be used to improve the SiPc solubility leading to solution processable OTFTs where the choice of axial group also dictates the thin film morphology an ultimately the resulting device performance.[5] GIWAXS studies show that processing conditions and choice of axial groups leads to changes in molecular alignment at the interface providing critical insight into device optimization.This presentation will cover our recent advances in the development of structure property relationships between SiPc structure, thin film processing and resulting charge transport properties.REFERENCES1. ACS Applied Materials & Interfaces. 2021, 13, 31321-313302. Organic Electronics. 2020, 87, 1059763. Advanced Electronic Materials. 2019, 5, 19000874. ACS Appl. Electron. Mater. 2021, 3, 5, 2212–22235. ACS Applied Materials & Interfaces. 2020, 13, 1008-1020 Figure 1

Subthreshold Conduction of Disordered ZnO-Based Thin-Film Transistors.

This study presents the disorderedness effects on the subthreshold characteristics of atomically deposited ZnO thin-film transistors (TFTs). Bottom-gate ZnO TFTs show n-type enhancement-mode transfer characteristics but a gate-voltage-dependent, degradable subthreshold swing. The charge-transport characteristics of the disordered semiconductor TFTs are severely affected by the localized trap states. Thus, we posit that the disorderedness factors, which are the interface trap capacitance and the diffusion coefficient of electrons, would result in the degradation. Considering the factors as gate-dependent power laws, we derive the subthreshold current-voltage relationship for disordered semiconductors. Notably, the gate-dependent disorderedness parameters are successfully deduced and consistent with those obtained by the gm/Ids method, which was for the FinFETs. In addition, temperature-dependent current-voltage analyses reveal that the gate-dependent interface traps limit the subthreshold conduction, leading to the diffusion current. Thus, we conclude that the disorderedness factors of the ZnO films lead to the indefinable subthreshold swing of the ZnO TFTs.

Low-Voltage Operated High DC Gain Amplification Stage Based on Large-Area Manufacturable Amorphous Oxide Semiconductor Thin-Film Transistor

The industry-standard amorphous metal–oxide–semiconductor (AOS) thin-film transistor (TFT) technology is demonstrated for making low-voltage high intrinsic gain devices. It is revealed by the technology computer-aided design (TCAD) simulation that, without need of making Schottky barrier contacts, large output resistance and high intrinsic gain can be achieved in a subthreshold regime for AOS TFTs. It is further proved by the measurement results with the fabricated AOS TFT from a Gen-4.5 manufacturing line. A simple single-stage zero- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{GS}}$</tex-math> </inline-formula> load amplifier is implemented as a proof of concept, achieving a voltage gain larger than 50 for weak signal detection at a supply voltage of 5 V.

56‐1: Invited Paper: Ultra‐high Frame Rate ADS LCDs

In recent years, LCD end‐users are putting forward higher and higher requirements for dynamic picture display realism. With the increase of display panel refresh rate, dynamic picture fidelity has a significant improvement. The extremely high refresh rate has become one of the most important indicators of high‐end display panels, especially for video game usage scenarios. However, the increase in refresh rate is a challenge to the drive capability of LCD semiconductor TFTs (Thin Film Transistor), the response time of liquid crystal, and the transmission of high‐frequency signals, resulting in the maximum refresh rate of high‐refresh‐rate displays currently on the market still at 240 ~ 300 Hz. In this paper, we solve the display distortion due to low charging ratio at ultra‐high refresh rate by improving GOA（Gate Driver on Array） driver circuit and applying high stability and high mobility bilayer oxide semiconductor technology. At the same time, the 1ms GTG (Gray to Gray) response time is achieved by testing and optimizing the pixel slit angle and cell gap of ADS (Advanced Super Dimension Switch) LCD, ensuring no image trailing at refresh rates up to 600 Hz. Then the anti‐electromagnetic interference ability of high‐speed signal is improved by high‐speed signal transmission quality enhancement technology. Through the application of the above technologies, we have developed the ultra‐high refresh rate IT display panel products such as 600Hz frame rate FHD NB LCD and 500 Hz FHD MNT LCD. And the 16.0” WUXGA 600Hz ADS LCD achieves the highest CMR 9000 rating in VESA latest dynamic picture CMR certification.

Theoretical Modeling of a Temperature-Dependent Threshold-Voltage Shift in Self-Aligned Coplanar IZTO Thin-Film Transistors

Here, we investigate the effect of increasing temperature on threshold voltage (VTH) stability in self-aligned coplanar amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs). An analytical model of the temperature dependency of VTH stability reveals the importance of device geometry and subgap density-of-state (DOS) reductions in highly stable a-IZTO TFTs. The validity of the analytical model is confirmed using experiments and technology computer-aided design simulations to predict quantitative relationships under various shifts in temperatures, subgap DOS, and VTH. The role of hydrogen impurity in performance and VTH stability is also examined. The incorporation of hydrogen in a-IZTO channels improves TFT performance and thermal stability (ΔVTH/ΔT = 3.18 mV/K) due to hydrogen’s role as a passivation center. However, excessive incorporation of hydrogen increases subgap DOS distribution, causing a slight deterioration in thermal stability (ΔVTH/ΔT = 3.31 mV/K). This suggests that hydrogen can be converted from a shallow donor to an acceptor-like deep trap state. Our findings inform future designs of stable oxide semiconductor TFTs in terms of thermal stability in emerging organic light-emitting diode, augmented and virtual reality, memory, logic, and monolithic three-dimensional applications.

Influence of indium doping on electrical performance of gallium oxide thin-film transistors

In the field of oxide semiconductor thin-film transistors (TFTs), the occurrence of charge trapping in the gate dielectric and interfaces presents significant challenges to their operational stability and reliability. In this study, we present high-performing amorphous Ga2O3 TFTs created using atomic layer deposition with varying indium doping concentrations. The channel length (Lch) and channel width (Wch) are 50 and 200 μm, respectively. As the Indium concentration increases from 0% to 60%, the charge trap density (Nit) decreases, resulting in a smaller hysteresis window. The TFTs with a doping concentration of 20% are particularly noteworthy, exhibiting high field-effect mobility (22.6 cm2 V−1 s−1), lower subthreshold swing (160 mV/dec) than amorphous Ga2O3 channel devices, a high on-off current ratio (109), an appropriate threshold voltage (−1 V), and a substantial output current (26 mA/mm at VGS = 16 V).

Super Flexible and High Mobility Inorganic/Organic Composite Semiconductors for Printed Electronics on Polymer Substrates

AbstractIn solution‐processed flexible electronics, it is challenging to obtain superior electrical and mechanical performance simultaneously. Attempts have been made to fabricate polymer doped oxide thin film transistors (TFTs), where, polymer doping frustrates the crystal structure of the parent oxide and causes amorphization. However, it also degrades the device mobility rapidly, thereby, limiting the allowable polymer content to only small values, which may not be sufficient for decisive enhancement in mechanical performance. In contrast, here an approach is proposed, where a set of water‐insoluble and chemically inert polymers are chosen to form inorganic/organic composite semiconductors. Herein, these selected polymers oppose a large degree of intermixing with the parent oxide lattice at the atomic scale, promote its crystallization, and help to maintain the electrical properties of the oxide semiconductors intact, even when they're in near‐equal amounts. Consequently, unaltered linear mobility of 40–45 cm2 V−1 s−1 can be obtained in In2O3‐based inorganic/organic composite semiconductor TFTs with a near‐equal weight of polymeric additives. Owing to the large polymer content, the TFTs are found to survive rigorous bending fatigue tests down to 1.5 mm bending radius without any deterioration in their electrical performance and without the formation of micro‐cracks in the composite semiconductor material.